With a quantum leap in VLSI technology in recent years, an SOI structure, which enables high-speed operation and low power consumption, has been attracting attention. In this technology, an active region (channel formation region) of a field-effect transistor (FET), which is conventionally formed with bulk single-crystalline silicon, is formed with a single-crystalline silicon thin film. It is known that use of the SOI structure enables manufacturing a MOS field-effect transistor with smaller parasitic capacitance than in the conventional case of using a bulk single-crystalline silicon substrate, and is advantageous to high speed operation.
As a method for manufacturing a conventional SOI substrate, a hydrogen ion implanting separation method is known (for example, refer to Reference 1: PCT International Publication No. 00/24059). In the hydrogen ion implanting separation method, a microbubble layer is formed at a given depth from a surface by implanting hydrogen ions into a silicon wafer to make the microbubble layer a cleavage plane, so that a thin single-crystalline silicon layer (SOI layer) is bonded to another silicon wafer; in addition to performing heat treatment for separating the SOI layer, Reference 1 describes that a bonding strength needs to be enhanced by forming an oxide film on the SOI layer by heat treatment in an oxidation atmosphere, removing the oxide film, and performing heat treatment in a reduction atmosphere at 1000 to 1300° C.
As an example of a semiconductor device utilizing an SOI substrate, a semiconductor device by the present applicant is known (refer to Reference 2: Japanese Published Patent Application No. 2000-12864). Reference 2 also discloses that heat treatment at temperatures of 1050 to 1150° C. is necessary in order to remove a level or a defect due to a stress in the SOI layer.